Can anyone explain how the dual ARM/RISC-V system works, architecturally?
Are there two actual CPUs on the same die? Is it one shared architecture with two different instruction decode stages, one for ARM and the other for RISC-V that can be toggled at boot time? I like the idea conceptually but I'm not sure how much of that is a hack and/or inefficient compared to a pure ARM or RISC-V core.
Can anyone explain how the dual ARM/RISC-V system works, architecturally?
Are there two actual CPUs on the same die? Is it one shared architecture with two different instruction decode stages, one for ARM and the other for RISC-V that can be toggled at boot time? I like the idea conceptually but I'm not sure how much of that is a hack and/or inefficient compared to a pure ARM or RISC-V core.
To be more precise, four CPUs - two ARM and two RISC. There is just a mux for the instruction and data buses - see chapter 3 of the [datasheet](https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.p...).
It’s space-inefficient as half of the CPUs are shutdown, but architecturally it’s all on the same bus.
It may be technically space inefficient but they only added the RISC-V cores because they had area to spare. It didn't cost them much.